发明名称 Semiconductor device with improved latch arrangement
摘要 The nonvolatile memory includes a nonvolatile memory circuit that possesses a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration, a program control circuit that writes information into the nonvolatile memory circuit, a volatile latch circuit that latches information read from the nonvolatile memory circuit, and a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuit. In response to the instruction of the readout operation, the readout control circuit supplies the operating voltage for the static latch operation to the nonvolatile memory circuit, and stops the supply of the operating voltage, after completing the latch operation.
申请公布号 US6529407(B2) 申请公布日期 2003.03.04
申请号 US20010880227 申请日期 2001.06.14
申请人 HITACHI, LTD. 发明人 SHUKURI SHOJI
分类号 G11C16/04;G11C16/06;G11C29/00;G11C29/04;H01L21/8244;H01L21/8247;H01L27/10;H01L27/105;H01L27/11;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/04 主分类号 G11C16/04
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