发明名称 |
COPPER PLATING METHOD OF VIA HOLE |
摘要 |
PURPOSE: To complete filling plating inside a via hole with ensured reliability in a short time, even if a hole diameter becomes as a small as 40 μm. CONSTITUTION: After chemical copper plating is applied to an inner surface of a via hole connecting upper and lower conductor layers of a multilayer substrate, the inside of a via hole is subjected to filling plating by electrolytic copper plating. The electrolytic copper plating is carried out first, at a low- current density of 1.5 A/dm¬2 or lower in an allowable current range of plating bath and thereafter the remaining plating is carried out at a higher current density (for example, 3A/dm¬2). Electrolytic copper plating is carried out by alternating positive pulse and negative pulse through pulse plating, whose energization amount of positive pulse is set large. Ratio t1/t2 of an energization time t1 for positive pulse and an energization time t2 for negative pulse is 40/2 and the ratio F/R of a current value F of positive pulse and a current value R of negative pulse is 1/3.
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申请公布号 |
KR20030014628(A) |
申请公布日期 |
2003.02.19 |
申请号 |
KR20020046628 |
申请日期 |
2002.08.07 |
申请人 |
KABUSHIKI KAISHA TOYOTA JIDOSHOKKI |
发明人 |
HIDAKA MASANOBU;INOUE TOSHIKI;KATO YOSHIFUMI;KUMAGAI KYOKO;SHIMO TOSHIHISA;YOSHIDA TAKASHI |
分类号 |
H05K3/46;H01L21/3205;H05K3/42;(IPC1-7):H01L21/320 |
主分类号 |
H05K3/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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