Repackaging semiconductor IC devices for failure analysis

摘要

The present invention provides a system and method for preparing semiconductor integrated circuits ("ICs"), particularly ball grid arrays ("BGAs"), quad flat packs ("QFPs") and dual in line packages ("DIPs") for failure analysis ("FA") using a variety of techniques, including emission microscopy ("EM") and externally induced voltage alteration ("XIVA"). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.