发明名称 METHOD FOR FORMING MULTILAYER METAL WIRING IN SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming a multilayer metal wiring in a semiconductor device is provided to be capable of reducing contact resistance between metal lines, improving the planarization of an interlayer dielectric and simplifying the processes. CONSTITUTION: After forming a lower metal wiring(11) on a substrate(10), a photoresist pattern(13) having a hole(19) is formed on the lower metal wiring. After hardening the photoresist pattern(13) by baking, a contact(17) is formed by filling a metal film into the hole. After removing the photoresist pattern, an interlayer dielectric(12) is formed on the exposed lower metal wiring(11). Then, an upper metal wiring(18) is formed on the resultant structure.
申请公布号 KR100368979(B1) 申请公布日期 2003.01.09
申请号 KR19950017714 申请日期 1995.06.28
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, BYEONG IL
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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