| 摘要 |
WN nodes (2 to 5) set the number of clocks in low-order 12 bits of cycle time data from cycle masters (20-50) to a bus counter (102A) and an internal counter (102B). When a control block is transmitted to the WN nodes (3 to 5), the WN node (2) stores a counted value of the counter (102B) in a cycle sync area. The WN nodes (3 to 5) which receive the control block extract the counted value from the cycle sync area, generate control information for correcting a difference so as to maintain an initial value by comparing the extracted counted value and the counted value of the above-mentioned counter (102A), and transmits such control information to the cycle masters (30 to 50). Thus, the number of clocks in the low-order 12 bits of the cycle time data in the cycle masters (30 to 50) is corrected, and a time synchronization among respective buses is established. Therefore, a time synchronization among a plurality of buses may be established satisfactorily.
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