DATA AND CLOCK RECOVERY CIRCUIT

摘要

PURPOSE: A data and clock recovery circuit is provided, which can make a clock synchronized to data in a fast time and does not need a phase locked loop per channel in a system for a multi channel serial data transmission and can reduce a chip area. CONSTITUTION: A reset signal generation part(10) generates a reset signal using a voltage controlled signal generated in a phase locked loop(PLL)(50) where the reset signal has a half pulse width of a data bit rate at every transition of inputted serial data. A clock signal generation part(20) comprises N clock signal generation blocks, and generates N clock signals using the voltage controlled signal generated in the PLL, and a delay time between the (N-1)th clock and the Nth clock is equal to a data bit rate of the input data. A phase control signal generation part(30) comprises N phase control signal generation blocks, and generates a phase control signal(PC(N)) controlling a phase of a clock(N) and then inputs it to a clock signal generation block(N), by receiving the reset signal and a clock(N-1) and a clock(N). And a flip flop part comprises (N-1) flip flops, and stores parallel data of (N-1) bit to the flip flop using (N-1) clocks.