发明名称 INSTRUCTION FOR ORDERING OF EXECUTION IN PIPELINE PROCESSING
摘要 PROBLEM TO BE SOLVED: To maximize a CPU performance in a multiprocessor computer system. SOLUTION: An ordering instruction to specify an execution order of other instruction improves a throughput in a pipelined multiprocessor. A restriction is imposed on a shared memory operation executed in the specified order. An execution order is maintained through a CPU register, an assignment of sequence numbers to instructions and a use of a system for hierarchical ordering. After reaching of previously specified instructions to specified execution states, the latter instructions are assured to reach the specified execution states. With ordering, it becomes possible for a partial memory operation on the CPU to be executed together with other memory operations not affected by such an execution. Accordingly, together with instructions specified to global memory operations, freedom of operations provided by the partial memory operation improves operation throughput for a shared multiprocessor computing environment.
申请公布号 JP2002324058(A) 申请公布日期 2002.11.08
申请号 JP20020074528 申请日期 2002.03.18
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 MCKENNEY PAUL E
分类号 G06F9/30;G06F9/38;G06F9/52;(IPC1-7):G06F15/177 主分类号 G06F9/30
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