| 摘要 |
The communication system stores packet data received via a plurality of communication channels in a memory or transmits packet data stored in the memory through the communication channels includes buffer descriptors in which information on packet data is stored. The system comprises a central processing unit (CPU) which stores the information on packet data in the buffer descriptors and indicates whether each of the buffer descriptors is being organized, whether an error occurred in packet data received, or whether the organization of each of the buffer descriptors is completed by allotting a flag bit to each of the buffer descriptors. The system comprises a direct memory access (DMA) controller which stops processing a buffer descriptor currently being accessed and accesses a next buffer descriptor, or processes packet data information stored in the buffer descriptor currently being accessed, after identifying the flag bit of the buffer descriptor currently being accessed.
|
