| 摘要 |
PURPOSE: To provide a lock detection circuit that optimizes a lock detection time and an unlock detection time of a PLL circuit. CONSTITUTION: The lock detection circuit is provided with counters 21, 22 that respectively receive a feedback signal and a reference signal received by a phase comparator 11 of the PLL circuit 10 and counts the signals, a comparator circuit 23 that provides an output of an active state control signal when the count of the counter 22 indicates a 1st value while a count of the counter 21 depicts a 1st value, a counter 24 that counts the feedback signal when the control signal outputted from the comparator circuit 23 is active, and a discrimination circuit 25 that outputs an output signal with a value denoting a lock state when the count of the counter 24 reaches a 2nd value. The comparator circuit 23 resets the counter 24 when the count of the counter 22 indicates no 1st value while the count of the counter 21 depicts the 1st value.
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