发明名称 INTERFACE CIRCUIT, LOGICAL CIRCUIT VERIFICATION METHOD, LOGICAL DEVICE, INFORMATION PROCESSING EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To solve such a problem that every conventional means for increasing the speed of the simulation of logical circuit requires the extraction process of specific circuit and the element for the determination, and the process thereof requires considerable design man-hours, and that a circuit different from the logical circuit, unlike the hardware model, is produced for performing the simulation, so that the time taken for the debug for the verification of validity thereof is generated. SOLUTION: This logical device is composed of a device A3 having a cycle of operation controlling mechanism 9, a device B4 composed of LSIA 46, LSIB 47, LSIC 48 equipped with interface circuits 10 that operate on different clocks respectively and have, like the device A3, the cycle of operation controlling mechanisms 9, and an other connected device 5 composed of a plurality of LSID 51s and LSIE 51s equipped with the interface circuits 10 having, like the device A3, the cycle of operation controlling mechanisms 9. Regarding the device A3, the device B4 and the other connected device 5, the data transmission between the device B4 and the device connected thereto is made in the same or a different cycle of operation.
申请公布号 JP2002229921(A) 申请公布日期 2002.08.16
申请号 JP20010029403 申请日期 2001.02.06
申请人 NEC KOFU LTD 发明人 SHINDO HISASHI
分类号 G01R31/28;G06F11/25;G06F13/10;G06F17/50;(IPC1-7):G06F13/10 主分类号 G01R31/28
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