| 摘要 |
A method and system for enhanced bus access in a multiprocessor system havin g multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each proces sor outputs a request to bus arbitration logic for a maximum-permitted number of sub-bus es. If the number of sub-buses granted to a particular processor equals the number of p ending transactions at that processor, all pending transactions are performed in pa rallel on separate sub-buses. If the number of sub-buses granted is less than the numb er of pending transactions, pending transactions are performed in a priority order . Finally, if the number of granted sub-buses is greater than the number of pending transactio ns, selected transactions are performed over multiple sub-buses in parallel, greatly enha ncing the speed of those transactions.
|
