Automatic bias adjustment circuit for use in PLL circuit

摘要

A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is opposite to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.