| 摘要 |
The present invention provides a data processing apparatus and method for controlling timing of transfer requests. The data processing apparatus comprises a bus for interconnecting a number of logic units, data being transferable between the logic units via the bus. A first logic unit is arranged to issue onto a bus a transfer request and a type signal indicating the type of the transfer request, and a second logic unit is arranged to receive the transfer request from the bus and to perform an operation in response to the transfer request. In accordance with the present invention, the first logic unit is arranged to encode within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit.By this approach, the performance of the data processing apparatus can be increased, since the performance of transfer requests can be governed directly by the actual performance of the logic unit issuing the transfer request.
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