Method of manufacturing integrated circuit package with cavity to expose lower conductive level

摘要

A method of manufacturing an integrated circuit package involves providing a multi-layered substrate (10) having a conductive layer (30) between two dielectric layers (20, 22), where a cavity is formed in one of the dielectric layers (22). The cavity exposes conductive layer (30) to enable coupling of integrated circuit (IC) chip (75) to the exposed portion of conductive layer (30). The conductive layer (30) may be coupled to bond pads on the IC chip (75) through wires (80). A ground plane or a power plane may be provided in the exposed portion of the conductive layer (30), which may also provide a connection for a signal line. The package may include a further conductive layer (32) above dielectric layer (22). The IC package may be a ball grid array (BGA) integrated circuit package having solder balls (65) connected to IC chip (75) by plated through holes in substrate (10).