| 摘要 |
A method and apparatus for speeding up the reading speed of a sequential I/O device, such as a Charge Coupled Device, is disclosed. The method involves in providing normal clocks for reading selected pixels and dummy clocks for reading unselected pixels. Since dummy clocks are faster than normal clocks, therefore the total time for processing the document can be less than using clocks of uniform speed. The apparatus of the invention comprises: a clock control device for generating two transfer pulses phi1 and phi2 in response to a clock cycle. The transfer pulses phi1 and phi2 are input to a sequential I/O device. The signal charge generated from the sequential I/O device will then output to an AND converter to be converted into digital signals. If the digital signals are marked, they will be latched. If not, they will simply be ignored.
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