| 摘要 |
In a variable resistance circuit included in a internal power supply potential generation circuit of a DRAM, to a fuse for tuning an internal power supply potential, an N channel MOS transistor is connected in parallel. In a pre-LT state return mode, a mode setting signal attains a "H" level to render the N channel MOS transistor conductive, so that the same state as that where no fuse is cut off is established to return the internal power supply potential to a level at a wafer test. It is therefore possible to quickly and accurately review wafer test conditions after a final test.
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