| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a write and read circuit of a variable length packet, which can read and write packets with high memory efficiency and can immediately read and write the next packet, when abolishment of packets is generated. SOLUTION: A variable length packet write circuit 2 is provided with a base register 12 for holding the address of a buffer memory 50, in which the top block of the variable length packet is written; a counter 6 in which increment is performed whenever the block is inputted; and an adder 114, which adds the address held in the base register 12 to the count value of the counter 6 and derives the address of a write destination of a buffer memory 50.</p> |
