发明名称 Linear capacitor structure in a CMOS process
摘要 A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plates.
申请公布号 US6351020(B1) 申请公布日期 2002.02.26
申请号 US19990438618 申请日期 1999.11.12
申请人 MOTOROLA, INC. 发明人 TARABBIA MARC L.;CHAN JOSEPH Y.;HALL GEOFFREY B.
分类号 H01L27/04;H01L21/822;H01L27/08;H01L29/94;(IPC1-7):H01L29/00 主分类号 H01L27/04
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