| 摘要 |
A synchronizing stage for synchronizing asynchronous signals provides for a signal stage to be connected in parallel with a clocked input stage and a holding stage that is clocked in anti-phase. The signal stage is clocked in anti-phase with the input stage. An output stage is connected downstream of the parallel circuit. The synchronizing stage reduces the probability of a metastable state in the event of overlapping and non-overlapping clock signals and ensures the reliable transfer of an input datum to the output of the synchronizing stage.
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