发明名称 |
A CRYPTOGRAPHIC ACCELERATOR |
摘要 |
A cryptographic accelerator (1) has a host interface (2) for interfacing with a host sending cryptographic requests and receiving results. A CPU (3) mangages the internal logical unit in an exponentiation sub-system (7) having modulator exponentiators (30). The exponentiators (30) are chained together up to a maximum of four, in a block (20). There are ten blocks (20). A scheduler uses control registers and an input buffer to perform the scheduling control.
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申请公布号 |
WO0129652(A3) |
申请公布日期 |
2002.01.10 |
申请号 |
WO2000IE00132 |
申请日期 |
2000.10.18 |
申请人 |
ACCELERATED ENCRYPTION PROCESSING LIMITED;FAIRCLOUGH, CHRISTOPHER;FLANAGAN, FRANCIS |
发明人 |
FAIRCLOUGH, CHRISTOPHER;FLANAGAN, FRANCIS |
分类号 |
G09C1/00;G06F7/72;(IPC1-7):G06F7/72;H04L9/30 |
主分类号 |
G09C1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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