| 摘要 |
A technique accurately calculates utilization information for an electronic design to help optimize the design. After synthesis of the complete design, information including number of combinatorial logic cells, maximum number of levels of combinatorial logic cells, number of registered logic cells, and number of latch logic cells for each line of source code is displayed. The information is in a source file text editor or in a graphic editor. The technique maps back from logic cells to technology-independent gates and back to lines of source code taking into account synthesized logic cells, and displays how many logic cells a line of source code is responsible for producing. For post-synthesis netlists having no synthesized logic cells, gates are grouped according to which logic cell they correspond. For netlists with synthesized logic cells, regions of logic cells within the netlist are first identified. Starting from a non-synthesized logic cell, its inputs are traversed upstream to form a region of logic cells until either an input pin is reached or another non-synthesized logic cell is reached. Regions may overlap. Synthesized logic cells within more than one region contribute a fraction to each region. Next, regions of gates are identified in the gate-level netlist that correspond to each region of logic cells. Logic cells of each region are distributed among gates of the corresponding region. Logic cells are counted for a line of source code by identifying to which gates the line corresponds and summing the logic cells for those gates.
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