| 摘要 |
<p>A semiconductor memory device 100 includes: a differential sense amplifier 9 having an input node 9a and an input node 9b, an information read section 110a, a reference section 110b, and a control section 140. The information read section 110a includes: a main bit line MBL coupled to the input node 9a; a select gate 4a; a sub-bit line SBL which is coupled to the main bit line MBL via the select gate 4a; a memory cell 1 which is coupled to the sub-bit line SBL and which is selectively activated in accordance with a voltage on a word line WL; a precharge section 120a for precharging the input node 9a and the main bit line MBL to a supply voltage Vdd; and a reset section 130b for resetting the sub-bit line SBL to a ground voltage Vss. The control section 140 controls the precharge section 120a, the reset section 130a, and the select gate 4a so that a portion of a charge which is precharged in the input node 9a and the main bit line MBL is redistributed to the sub-bit line SBL after precharging the input node 9a and the main bit line MBL to the supply voltage Vdd and resetting the sub-bit line SBL to the ground voltage Vss. <IMAGE></p> |
