发明名称 TEST METHOD FOR SEMICONDCUTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for conducting a production test considering failure by the effect of cross talk and make the production test pattern considering the failure by the effect of cross talk with a minimum number of patterns. SOLUTION: A net list 1 fulfilling a logic function is input, a scan path test structure is installed (S1) and the net list is layout in a mask pattern (S2). Danger locations apt to be affected by the cross talk in the layout are extracted (S3) and to the extracted danger locations, test circuits are added (S4) to form test patterns apt to be affected by the cross talk with a gate delay ATPG. A production test is conducted (S6, 7) by using the test pattern produced by applying the gate delay ATPG (S5) on the circuit.
申请公布号 JP2001305191(A) 申请公布日期 2001.10.31
申请号 JP20000125455 申请日期 2000.04.26
申请人 NEC MICROSYSTEMS LTD 发明人 ASO MASAO
分类号 G01R31/28;G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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