发明名称 TEST METHOD AND TEST DEVICE FOR SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor memory at a low cost. SOLUTION: A discrimination voltage supplying circuit 2 generates read- voltage under control of a control circuit 1, and supplies it to a memory cell array 7 through a word line Wi decided by address data Address. A discriminating circuit 6 obtains data read out at the time through a Y selector 5 and a sense amplifier 8, and holds it. The decision voltage supplying circuit 2 generates determine-verify voltage between read-voltage and write-verify voltage, and supplies it to the memory cell array 7 in the same way. The decision circuit 6 compares data read out at the time with data previously held. When a storage element of the memory cell array 7 is deteriorated and a threshold value of gate voltage is reduced, data cannot be read out correctly by the determine- verify voltage, the comparison result in the decision circuit 6 is noncoincidence.</p>
申请公布号 JP2001266599(A) 申请公布日期 2001.09.28
申请号 JP20000076461 申请日期 2000.03.17
申请人 NEC MICROSYSTEMS LTD 发明人 MASAKI TORU
分类号 G01R31/26;G01R31/28;G06F12/16;G11C17/00;G11C29/00;G11C29/50;(IPC1-7):G11C29/00 主分类号 G01R31/26
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