| 摘要 |
PURPOSE: A reset signal control circuit of a flash memory is provided to stabilize a re-execution operation by disabling the PDONE signal of an initial reset order when a re-execution order is inputted in the time of an enable of the PDONE signal. CONSTITUTION: When a present state is a temporary holding state, a temporary holding signal(SUSb) is a low signal. The temporary holding signal(SUSb) is inputted to the other terminal of an NOR gate(NO2) and one terminal of an NOR gate(NO3). At this time, when a write enabling signal(WEb) is a low state, the NOR gate(NO2) outputs a high signal. The high signal of the NOR gate(NO2) means that the present state is the temporary holding state, and that an external order is inputted. When the NOR gate(NO2) outputs the high signal, each of a non-inverting terminal(Q) of the second flip-flop(FF2) and an inverting terminal(Qb) of the third flip-flop(FF3) outputs a high signal. Meanwhile, the write enabling signal(WEb) in the low state is delayed by a delay part(10), and is inputted to one input terminal of an NAND gate(ND3). At this time, because the other input terminal of the NAND gate(ND3) receives a high signal, the NAND gate(ND3) outputs a high signal to one input terminal of an NAND gate(ND4). At this time, because the high signal of the inverting terminal(Qb) is inputted through the other input terminal of the NAND gate(ND4), the NAND gate(ND4) outputs the second control signal(Real_PDONE) in a low state. If the write enabling signal(WEb) is changed into a high state, the NOR gate(NO2) outputs a low signal, and the second flip-flop(FF2) outputs a low signal through the non-inverting terminal(Q), and the third flip-flop(FF3) outputs a low signal through the inverting terminal(Qb).
|
