| 摘要 |
PROBLEM TO BE SOLVED: To improve the transfer efficiency of data and to enable high-speed burst data transmission by reducing idle time not to utilize a data bus. SOLUTION: This system is provided with an address buffer 2 for fetching an address (c) synchronously with a clock, a burst counter 3 for generating the address of a burst length, a row address register 4 for controlling timing by latching a row address, a column address register 5 for controlling timing by latching a column address, a row address decoder 6 for decoding the row address, a column address decoder 7 for decoding the column address, a mode register 8 for setting the operating mode of a DRAM, a command decoder 9 for analyzing/deciding a command based on a control signal (d), a control circuit 10 for controlling the operation of the entire DRAM, a memory array 11 for preserving data (e) and a data input/output buffer 15 for exchanging the data (e).
|
