| 摘要 |
PURPOSE: A method for manufacturing a dynamic random access memory(DRAM) device is provided to prevent an open fail of an interlayer interconnection in core and peripheral regions, by using a conductive material of a cell array region or conductive material used only in the core and peripheral regions to form the interlayer interconnection before the bit line is formed. CONSTITUTION: Transistors having sources, drains and gates are formed on a semiconductor substrate(100) wherein the cell array region, the core region and the peripheral region are formed. The first insulation layer is formed on the substrate including the gates. A conductive pad for the bit line(130) electrically connected to the drain/source of at least one transistor formed in the cell array region is formed while the interlayer interconnection(122) corresponding to the bit line electrically connected to at least one transistor formed in the core and peripheral regions is formed. The second insulation layer is formed on the first insulation layer including the conductive pad and the interlayer interconnection. A plug(126) for a cell capacitor storage electrode(136) penetrates the second and first insulation layers and is electrically connected to the source/drain of the transistor in the cell array region. A conductive layer for the bit line penetrates the second insulation layer and is electrically connected to the conductive pad. A capping layer surrounds the conductive layer exposed to the upper portion of the second insulation layer. The cell capacitor storage electrode is formed on the second insulation layer, electrically connected to the plug.
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