发明名称 |
Method of producing a memory cell configuration |
摘要 |
A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.
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申请公布号 |
US6180458(B1) |
申请公布日期 |
2001.01.30 |
申请号 |
US19980095260 |
申请日期 |
1998.06.10 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
KRAUTSCHNEIDER WOLFGANG;HOFMANN FRANZ;ROESNER WOLFGANG |
分类号 |
H01L21/8246;H01L27/112;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/8246 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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