发明名称 |
Low power wordline decoder circuit with minimized hold time |
摘要 |
A wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.
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申请公布号 |
US6172531(B1) |
申请公布日期 |
2001.01.09 |
申请号 |
US19990251089 |
申请日期 |
1999.02.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AIPPERSPACH ANTHONY GUS;FREIBURGER PETER THOMAS |
分类号 |
G11C8/08;G11C8/10;H03K19/096;(IPC1-7):H03K19/094 |
主分类号 |
G11C8/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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