发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
<p>In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.</p> |
申请公布号 |
EP1058310(A2) |
申请公布日期 |
2000.12.06 |
申请号 |
EP20000111706 |
申请日期 |
2000.05.31 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
YAMAZAKI, SHUNPEI;SUZAWA, HIDEOMI;YAMAGATA, HIROKAZU |
分类号 |
G02F1/1362;H01L21/336;H01L21/77;H01L27/12;H01L27/32;(IPC1-7):H01L27/12;H01L21/84 |
主分类号 |
G02F1/1362 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|