| 摘要 |
PURPOSE: A circuit for controlling output driving of RAM bus DRAM is provided to decrease a driving size of a gate voltage generating unit and a gate voltage distributing unit and to decrease a size of a circuit by quickly charging an input line of an output driving unit for receiving a gate voltage level when adjusting a current. CONSTITUTION: A current control unit(10) measures real voltage levels(VOH,VOL) and increases or decreases a current control counter to generate a current control signal for adjusting a current amount of an output driving unit(16). A gate voltage generating unit(11) generates a gate voltage. A gate voltage distributing unit(12) multiplexes a time clock enable signal and the current control signal generated in the current control unit(10) according to the gate voltage generated in the gate voltage generating unit(11) and provides the multiplexed voltage to an upper device of the output driving unit(16). A slew rate control unit(13) generates control codes(sl1,sl2) so that a slew rate is constant regardless of a power, a voltage and a temperature. A phase dividing unit(14) generates an inputted time clock(tclk) as clocks(tclkl,tclkb) having the phase difference with 180°C. A multiplexer and pre-driver(15) is synchronized to clocks(tclkl,tclkb) outputted from the phase dividing unit(14) to output an inputted data to an output driving unit(16) or outputs voltages(q,ql) provided to a lower device of the output driving unit(16) according to control codes(sl1,sl2) provided from the slew rate control unit(13). The output driving unit(16) turns on or off the n number of MOS transistors according to a voltage(envg) distributed in the gate voltage distributing unit(12) and voltages(q,ql) outputted from the multiplexer and pre-driver(15).
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