Method of manufacture of test circuit on silicon wafer, comprising masking with reticle for integrated circuits and test circuit, in stages with shielding and exposing test circuit by diaphragm

摘要

The manufacturing method comprises the stages of exposure of silicon wafer containing a set of integrated circuits and at least one test circuit, with the intermediary of a reticle laid out in a chamber containing a diaphragm for shielding non-used parts of reticle. The procedure comprises the exposure stage carried out with at least one reticle (130) comprising conjointly a mask (132) for integrated circuits. The exposure stage comprises one or more steps in the course of which the mask (133,134,135) for the test circuit is shielded by the diaphragm, and at least one step when the mask is exposed by the diaphragm, during which all or a part of the mask for the integrated circuits is shielded by the diaphragm. The exposure stage comprises at least one step when the first area of silicon wafer is exposed during which the mask (133,134,135) for the test circuit is shielded by the diaphragm, and at least one step when the second area of silicon wafer is exposed during which the mask for the test circuit is uncovered by the diaphragm. The mask (132) for the integrated circuits comprises a set of elementary masks (132-1,..., 132-30) laid out in rows and columns, each elementary mask corresponding to an integrated circuit. All or a part of the mask (132) for integrated circuits is shielded by the diaphragm in the course of exposure of the second area. The mask for the test circuit comprises a set of elementary masks (133,134,135), each elementary mask corresponding to a test circuit. The test circuits are regrouped in one or more areas of the silicon wafer. The integrated circuits are the radio-frequency (RF) test circuits, and the test circuits comprise etalon or standard circuits with etalon impedance loads for the calibration of probe for electrical testing of RF integrated circuits. The etalon circuits comprise each at least one elementary structure containing two contact pads deposited on an insulating layer, at least one etalon load measurable from the contact pads, and a conducting screen on insulating layer. The conducting screen is connected to one contact pad. The etalon circuit comprises two etalon loads connected in series with midpoint connected to the conducting screen. The etalon circuit comprises at least one supplementary contact pad for an access to the midpoint of etalon loads.