发明名称 FUNCTION SYNTHESIS METHOD, FUNCTION SYNTHESIS DEVICE AND RECORDING MEDIUM THEREFOR
摘要 PROBLEM TO BE SOLVED: To generate a logic circuit indicating an operation result capable of being easily compared with the executed result of a program. SOLUTION: A data flow graph is generated based only on the arithmetic sentence of a C program (S1). The data flow graph is divided and state names are allocated respectively (S2). An arithmetic operation for outputting the value of an observation variable is detected from the data flow graph, the state name of executing the arithmetic operation and the observation variable are stored in an observation variable-state list (S3) and an FSM(finite state machine) is generated (S4). In the FSM, to a control signal line corresponding to respective states in the list, the output terminal of an RT level description is added (S5). A data path is generated (S6) and the output terminal of the RT level description is added to a signal line corresponding to the respective observation variables in the list in the data path (S7). The FSM and the data path are connected and RT level data are generated (S8).
申请公布号 JP2000242684(A) 申请公布日期 2000.09.08
申请号 JP19990045447 申请日期 1999.02.23
申请人 NEC CORP 发明人 OOTSUBO MOTOHIDE
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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