| 摘要 |
PURPOSE: A frequency multiplier is provided to be capable of reducing a layout area occupied by the frequency multiplier by reducing a dimension of a delay part. CONSTITUTION: A clock signal(CLK) is supplied to an exclusive NOR gate(XNOR1) through a direct path and a delay path via a delay part(4). An output signal(D1) of the delay part(4) has a 1/4-shifted phase of the clock signal(CLK). An output signal of the gate(XNOR1) is supplied to an exclusive NOR gate(XNOR2) through a direct path and a delay path via a delay part(5). An output signal(D2) of the gate(XNOR2) has a 1/4-shifted phase of an output signal of the gate(XNOR1). An output signal of the gate(XNOR2) is supplied to an exclusive NOR gate(XNOR3) through a direct path and a delay path via a delay part(6), which makes a delay time reduced by a half as compared with the delay part(5).
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