| 摘要 |
<p>A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle. A sensing circuit is coupled to the multibit memory cell which compares current from the multibit memory cell to a first reference current and a second reference current, and produces a first output during the first time interval having a first logic state when the current from the cell exceeds the first reference current and a second logic state if the current from the cell is less than the first reference current, and produces a second output during the second time interval having a first logic state if the current from the cell is less than the second reference current and greater than the first reference current, and a second logic state if the current from the cell is greater than the first reference current and greater than the second reference current, or less than the first reference current. <IMAGE></p> |
