DELAY LOOKED LOOP WITH VARYING CLOCK DELAY AND SEMICONDUCTOR MEMORY DEVICE USING DELAY LOOKED LOOP

摘要

PURPOSE: A delay locked loop with varying clock delay is provided wide active frequency range. And a memory device is provided by using the delay locked loop. CONSTITUTION: A phase detector(311) receives Reference Clock signal(RCLK) and Feedback Clock Signal(FDCLK) from delay complementary circuit(341). The phase detector(311) compares the phase of two signals and generate up or down signal. A charge pump(321) produces direct current voltage(VCON) based on the signals of pause detector(311). If the up signal is generated, the VCON is higher than reference level. If the down signal is produced, the VCON is lower than reference level. A variable delay circuit(331) receives and delays PCLK under controlling of VCON from the charge pump(321), power up signal(PVCCH), and synchronous signal(DLLST). The variable delay circuit(331) has many delay units. After passing the variable delay circuit(321), the RCLK is changed advanced clock signal(ADCLKN) with variant delay time. The delay time is depend on the number of operating delay units. The phase detector(311) compares the phase of RCLK and ADCLKN(or FDCLK) and adjusts the number of delay units in the variable delay circuit(331) to reduce phase difference of the two signals. Using the delay locked loop(301) in semiconductor memory device, the memory device is managed to active frequency range without altering inner circuit.