ADDRESS GENERATOR FOR READ OPERATION IN BLOCK INTERLEAVER

摘要

PURPOSE: An address generator for read operations in a block interleaver is provided to offer an efficient address generator to read the addresses of an interleaver. CONSTITUTION: An address generator for read operations in a block interleaver generates an address using an n-bit memory and selecting one of the n bits. The address generator is composed of an address counter and a bit selection counter. The address counter generates an address for a block composed of combinations of a plurality of counters. The bit selection counter generates an address for a specific bit in the block.