| 摘要 |
Semiconductor memory device, comprising at least one memory cells row, each memory cell comprising an information storing element (2) and a related select transistor (1) for selecting the storing element (2). The select transistor (1) comprises a gate oxide region (11) over a silicon substrate (14), a lower polysilicon layer (10) and an upper polysilicon layer (6) superimposed to the gate oxide region (11) and electrically insulated therebetween by an intermediate dielectric layer (9) interposed between them. The gate oxide regions (11) of the select transistors (1) of the at least one row are separated by field oxide regions (15), and the lower and upper polysilicon layers (10,6) and the intermediate dielectric layer (9) extend along the row over the gate oxide regions (11) of the select transistors (1) and over the field oxide regions (15). Along the row it is provided at least one opening in the upper polysilicon layer (6), intermediate dielectric layer (9) and lower polysilicon layer (10), inside of which a first contact element (20) suitable to electrically connect the lower and upper polysilicon layers (6,10) is inserted. <IMAGE> |
