| 摘要 |
The present invention proposes a method and apparatus for compensating for the spatial variation across the surface of a wafer in certain design parameters of semiconductor devices. The spatial variation in the design parameters is due to the spatial variation in some of the processes involved in the manufacturing of the devices upon the semiconductor wafer. Using metrology tools, the physical, chemical, and electrical parameters of the devices across the surface of the wafer are first measured and recorded. These device parameters include the certain design parameters that must remain within certain design limits or that are to be optimized. Examples of these design parameters for a transistor are the threshold voltage, the switching speed, and the current consumption. The spatial variation in the design parameters may be compensated by altering the doping profile across the wafer with some of the implantation steps. For example, heavier doping may be used for the source/drain regions of transistors close to the center of the wafer compared to doping for the source/drain regions which are close to the perimeter of the wafers. A computer model of the devices is used to determine the appropriate ion implantation profile for one or more implantation steps that would compensate for the spatial variation of the design parameters. Ion implantation is chosen for the compensation because the implantation dosage and energy can be accurately controlled, and because the ion implanters can be easily reprogrammed to deliver different amounts of dosages and energies in each region of the wafer. Small changes in the ion implantation doping profile are made for the next set of wafers and the device parameters along with the design parameters are remeasured.
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