Test pattern generator for high-speed semiconductor memory test, generating test patterns based on control instructions read from address produced by address expander

摘要

Test pattern generator includes a control memory (32) for storing control instructions, and a vector memory (12) for storing vector instructions which indicate a sequence of control instructions. An address expander (22) generates an address of each control instruction in accordance with vector instructions stored in group memories (16). Test pattern calculator (36) generates test patterns based on the control instructions read from address produced by address expander. An Independent claim is provided for a corresponding test pattern generating method.