| 摘要 |
A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node (26PN, 28PN, 30PN) to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path (26L and 26DT, 28L and 28DT, 30L and 30DT) conrected to the precharge node Each discharge path is operable in response to at least one enabling input signal (INPUTS26, INPUTS28, INPUTS30) to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter (26INV, 28INV, 30INV) coupled to the precharge node and having an output for providing a second monotonic transitioning data signal. The second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal. The dynamic multiplexer further comprises the integer number N of data select paths. Each of the data select paths comprises a select transistor T1, T2, T3), the transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal (SEL1, SEL2, SEL3). A drain of the select transistor in each of the data select paths is coupled to conditionally discharge an output precharge node (DSELPN). Lastly, the dynamic multiplexer includes an output inverter (INVDOUT) having an input connected to the output precharge node. In a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.
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