发明名称 Verpackte Halbeiteranordnung und deren Herstellungsverfahren
摘要 For manufacturing a packaged semiconductor device, a lead frame (8) with an electrically insulating strip member (70) and a semiconductor chip (4) is placed in a molding unit having upper and lower dies (11a,11b). The upper and lower dies (11a,11b) have recessed areas (a,b) for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies (11a,11b). The lead frame (8) is positioned so that a surface of each lead (5) with the insulating strip (70) member applied thereto is contacted with one (11a) of the upper and lower dies having a larger recessed area and a molding line (ML) of the molding unit intersects the insulating strip member (70). The molding unit is closed to clamp the lead frame (8) to depress and thrust into spaces between adjacent leads that part of the strip member (70) which is outside the molding line and to form the cavity of the molding unit. By injecting a molding material into the cavity, a molding package (2) is provided encapsulating the semiconductor chip and a portion of each lead. The packaged semiconductor device (1) has a flanged side surface (S3) with an insulating strip (7) provided between a step (SS) of the flanged side surface and intermediate portions (Li) of the leads (5) which are between first portions (L1) of the leads encapsulated in the molding package (2) and second portions (L2) of the leads protruding from the flanged side surface. An insulating filler (7') is provided in spaces between those parts of the second portions of the leads which outwardly adjoin the intermediate portions of the leads. <IMAGE> <IMAGE>
申请公布号 DE69419881(T2) 申请公布日期 2000.03.16
申请号 DE1994619881T 申请日期 1994.12.07
申请人 HITACHI, LTD. 发明人 KISHIKAWA, NORIO;YOSHIDA, IKUO;HAYASHIDA, TETSUYA
分类号 B29C45/26;B29C45/02;B29C45/14;B29L31/34;H01L21/56;H01L23/28;H01L23/31;H01L23/495;H01L23/50 主分类号 B29C45/26
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