发明名称 DELAY CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a delay circuit for reducing a through current and current consumption and reducing noise affecting a power source and the ground. SOLUTION: In this delay circuit, a high level output block 1 outputs a high level potential when input signals are at a low level, a low level output block 2 outputs a low level potential when the input signals are at a high level and the high level potential and the low level potential are delayed for prescribed time in an analog delay element part 3. The delay signals of the high level are outputted at the low level by the low level output block 5 of an output buffer part B and the delay signals of the low level are outputted at the high level by the high level output block 4 of the output buffer part B. Immediately after the levels of the output signals of the low level output block 5 and the high level output block 4 change, a level amplification part 6 positively feeds back the output level of the analog delay element part 3 in terms of the level to the output value of the output buffer part B.</p>
申请公布号 JP2000059186(A) 申请公布日期 2000.02.25
申请号 JP19980221424 申请日期 1998.08.05
申请人 NEC CORP 发明人 BABA FUJIO
分类号 H03F1/34;H03K5/14;H03K19/0175;(IPC1-7):H03K5/14;H03K19/017 主分类号 H03F1/34
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