| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the complexity in the design and control of a reference cell by comparing charge states with each other, and by generating a two-bit signal for coding the charge states by the output. SOLUTION: In the case of both erased memory cells, even when cells F1 and F2 adsorb different current, mirroring is made in first and second current mirror circuits 19, 20, 33, and 34, and voltages 01 and 02 are set to a high level for corresponding to a logic state '11'. In the written cells F1 and F2, the cells do not adsorb current, and current being mirrored in first and second current mirror circuits 19, 20, 22, and 23 is insufficient to reduce the voltage in I/O nodes 41a and 41b. The output voltages 01 and 02 correspond to a logic state '00'. In the case of the cells F1 and F2 being similarly erased and written, respectively, and in the case of the cells F1 and F2 being written and erased, respectively, the each logic state is set to '10' or '01'.</p> |
