发明名称 |
DESIGNING METHOD OF SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To facilitate the breaking of an evaluating circuit while sustaining the functions of a proper circuit of a semiconductor element including the evaluating circuit, so as to make feasible of annexing the evaluating circuit without affecting the operations of the proper circuit. SOLUTION: A circuit containing a proper circuit 402 and an evaluating inner cell 405 directly connecting to the proper circuit 402 is laid out. Next, a proper I/O pad 403 is shifted for securing an evaluating arrangement region so as to arranged an evaluating circuit in this space. Finally, an evaluating inner cell 405 and an evaluating circuit 406 are connected by an evaluating wiring 408 using a new layer, not using a proper wiring 404 according to the circuit connection data.
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申请公布号 |
JP2000036562(A) |
申请公布日期 |
2000.02.02 |
申请号 |
JP19980202397 |
申请日期 |
1998.07.17 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
ICHINOMIYA TAKAHIRO;FUJINO KENYA |
分类号 |
H01L21/822;H01L21/82;H01L27/04;(IPC1-7):H01L27/04 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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