| 摘要 |
An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM0-REM3. The check remainder bytes REM0-REM3 are utilized to generates syndromes S1, S3 and a factor SB, the syndromes in turn being used to obtain either one or two error location positions ( alpha L1, alpha L2). The mathematical calculation circuit (104) not only generates the syndromes S1, S3 and factor SB, as well as the error location positions ( alpha L1, alpha L2), but also generates the addresses of the bit errors in the sector (L1-64 [complemented], L2-64 [complemented]. |
