| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a mask layout pattern data verification device) capable of efficiently executing detailed circuit simulation. SOLUTION: A semiconductor verification device 20 (mask layout pattern data verification device) includes a path retrieving part 3 for retrieving a path from a specified I/O net to a power supply or ground, a parasitic element extraction part 4 for extracting a parasitic element on the path, a probe point recognition part 8 for recognizing a net pointed out by a probe point as a floating net, an automatic floating net connection part 9 for connecting the floating net to the power supply or the ground when the input to a device for inputting the floating net can be uniquely determined, a succeeding step gate capacity discriminating part 10 for extracting a parasitic element including a transistor of a succeeding step when a net to be inputted to the transistor of the succeeding step is a floating net, and a net list output part 5 for outputting a net list to a net list file 6.</p> |
