发明名称 Circuit and method of latching a bit line in a non-volatile memory
摘要 A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38, 44) each having outputs respectively coupled to bit lines (50, 54, 56), and control inputs coupled to a common control line (132). The bit lines each include a latch (60, 62, 64) that is set to provide a programming voltage (VPP) during write mode. The bit lines have serial switches (78, 80, 82) that break continuity when writing to the latches. The bit line latches are made transparent to the bit lines during read mode. The common control line is coupled through a programming transistor (130) to an erase line (72). The erase line must be driven to a programming voltage during erase mode. The erase line uses one of the bit line latches to provide its programming voltage.
申请公布号 US5978262(A) 申请公布日期 1999.11.02
申请号 US19980009290 申请日期 1998.01.20
申请人 MOTOROLA, INC. 发明人 MARQUOT, ALEXIS;TARBOURIECH, JEAN-CLAUDE;DECHAMPS, PAUL
分类号 G11C16/10;G11C16/12;(IPC1-7):G11C16/14 主分类号 G11C16/10
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