| 摘要 |
A FIFO single port storage device and methods for using the same are disclosed. The FIFO device includes a single port memory for storing data from a host processor. The single port memory is addressed in a sequential and non-random manner, possibly by a monotonically increasing counter. Control circuitry coupled to the counter and the memory allows for the reading/writing of host data from/to the single port memory. Write protect circuitry prevents host writes to the single port memory by entering a write protect state under combinations of the following conditions: (1) the FIFO is full; (2) the FIFO is nearly full, as defined by a host programmable threshold; (3) the host processor commands the FIFO to enter the write protect state; or (4) the host processor acknowledges a FIFO nearly full interrupt. The errant, or stray, write detection circuitry sets a status flag if a write occurs while the FIFO is in the write protect state. The errant write detection circuity detects stray writes to the memory based on the write protect state value and the quantity of data stored in the FIFO, independent of any particular range of memory protected. Information is read from the FIFO by entering the write protect state, determining the quantity of stored FIFO data, reading the data, and resetting the quantity of data to zero. The FIFO device may be implemented using a field programmable gate array, or FPGA.
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