Collar etch method to improve polysilicon strap integrity in DRAM chips

摘要

In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO2/Si3N4 and polysilicon selectively (i.e. which etches TEOS SiO2 faster than Si3N4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C4F8/Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si3N4 pad layer is reached (this can be accurately detected), the etch is continued a short period of time to ensure the complete removal of the horizontal portions of the collar layer, including at the trench bottom, but not the vertical portions in the trench sidewalls.